SMJ320C6701-SP Datasheet, PDF (31/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
Switching Characteristics for CLKOUT2⁽¹⁾
(see Figure 10)
NO.
1
2
3
4
t_c(CKO2)
t_w(CKO2H)
t_w(CKO2L)
t_t(CKO2)
PARAMETER
Cycle time, CLKOUT2
Pulse duration, CLKOUT2 high
Pulse duration, CLKOUT2 low
Transition time, CLKOUT2
(1) P = 1/CPU clock frequency in ns.
(2) This parameter is not tested.
MIN
2P – 0.7⁽²⁾
P – 0.7⁽²⁾
P – 0.7⁽²⁾
MAX
2P + 0.7⁽²⁾
P + 0.7⁽²⁾
P + 0.7⁽²⁾
0.6 ⁽²⁾
UNIT
ns
ns
ns
ns
CLKOUT2
1
4
2
3
4
Figure 10. CLKOUT2 Timing
SDCLK, SSCLK Timing Parameter
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
Switching Characteristics for the Relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO.
1
2
3
4
t_{d(CKO1–SSCLK)}
t_{d(CKO1–SSCLK1/2)}
t_{d(CKO1–CKO2)}
t_{d(CKO1–SDCLK)}
PARAMETER
Delay time, CLKOUT1 edge to SSCLK edge
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
Delay time, CLKOUT1 edge to CLKOUT2 edge
Delay time, CLKOUT1 edge to SDCLK edge
MIN
–0.8
–1
–1.5
–1.5
MAX
3.4
3
2.5
1.9
UNIT
ns
ns
ns
ns
CLKOUT1
1
SSCLK
2
SSCLK (1/2rate)
3
CLKOUT2
4
SDCLK
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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