SMJ320C6701-SP Datasheet, PDF (44/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
SGUS030E – APRIL 2000 – REVISED JULY 2009 ............................................................................................................................................................ www.ti.com
EXTERNAL INTERRUPT/RESET TIMING
Timing Requirements for Interrupt Response Cycles⁽¹⁾⁽²⁾
(see Figure 26)
NO.
2
3
t_w(ILOW)
t_w(IHIGH)
Width of the interrupt pulse low
Width of the interrupt pulse high
MIN
2P ⁽³⁾
2P ⁽³⁾
MAX
UNIT
ns
ns
(1) Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus,
they can be connected to asynchronous inputs.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3) This parameter is not tested.
Switching Characteristics During Interrupt Response Cycles⁽¹⁾
(see Figure 26)
NO.
1
4
5
6
t_{R(EINTH–IACKH)}
t_{d(CKO2L–IACKV)}
t_{d(CKO2L–INUMV)}
t_{d(CKO2L–INUMIV)}
PARAMETER
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 x CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
MIN
9P
–0.5P
–0.5P
MAX
13 – 0.5P
10 – 0.5P
UNIT
ns
ns
ns
ns
CLKOUT2
2
EXT_INTx, NMI
Intr Flag
IACK
INUMx
1
3
4
4
6
5
Interrupt Number
Figure 26. Interrupt Timing
44
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