SMJ320C6701-SP Datasheet, PDF (37/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
SYNCHRONOUS DRAM TIMING
Timing Requirements for Synchronous DRAM Cycles
(see Figure 18)
NO.
7
8
t_{su(EDV–SDCLKH)}
t_{h(SDCLKH–EDV)}
Setup time, read EDx valid before SDCLK high
Hold time, read EDx valid after SDCLK high
MIN
2
3
MAX
UNIT
ns
ns
Switching Characteristics for Synchronous DRAM Cycles⁽¹⁾
(see Figure 18 – Figure 23)
NO.
1
2
3
4
5
6
9
10
11
12
13
14
15
16
17
18
t_{osu(CEV–SDCLKH)}
t_{oh(SDCLKH–CEV)}
t_{osu(BEV–SDCLKH)}
t_{oh(SDCLKH–BEIV)}
t_{osu(EAV–SDCLKH)}
t_{oh(SDCLKH–EAIV)}
t_{osu(SDCAS–SDCLKH)}
t_{oh(SDCLKH–SDCAS)}
t_{osu(EDV–SDCLKH)}
t_{oh(SDCLKH–EDIV)}
t_{osu(SDWE–SDCLKH)}
t_{oh(SDCLKH–SDWE)}
t_{osu(SDA10V–SDCLKH)}
t_{oh(SDCLKH–SDA10IV)}
t_{osu(SDRAS–SDCLKH)}
t_{oh(SDCLKH–SDRAS)}
PARAMETER
Output setup time, CEx valid before SDCLK high
Output hold time, CEx valid after SDCLK high
Output setup time, BEx valid before SDCLK high
Output hold time, BEx invalid after SDCLK high
Output setup time, EAx valid before SDCLK high
Output hold time, EAx invalid after SDCLK high
Output setup time, SDCAS valid before SDCLK high
Output hold time, SDCAS valid after SDCLK high
Output setup time, EDx valid before SDCLK high
Output hold time, EDx invalid after SDCLK high
Output setup time, SDWE valid before SDCLK high
Output hold time, SDWE valid after SDCLK high
Output setup time, SDA10 valid before SDCLK high
Output hold time, SDA10 invalid after SDCLK high
Output setup time, SDRAS valid before SDCLK high
Output hold time, SDRAS valid after SDCLK high
MIN
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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