SMJ320C6701-SP Datasheet, PDF (34/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
SGUS030E – APRIL 2000 – REVISED JULY 2009 ............................................................................................................................................................ www.ti.com
SYNCHRONOUS-BURST MEMORY TIMING
Timing Requirements for Synchronous-Burst SRAM Cycles (Full-Rate SSCLK)
(see Figure 14)
NO.
7
8
t_{su(EDV–SSCLKH)}
t_{h(SSCLKH–EDV)}
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
MIN
2.6
1.5
MAX
UNIT
ns
ns
Switching Characteristics for Synchronous-burst SRAM Cycles⁽¹⁾ (Full-Rate SSCLK)
(see Figure 14 and Figure 15)
NO.
1
2
3
4
5
6
9
10
11
12
13
14
15
16
t_{osu(CEV–SSCLKH)}
t_{oh(SSCLKH–CEV)}
t_{osu(BEV–SSCLKH)}
t_{oh(SSCLKH–BEIV)}
t_{osu(EAV–SSCLKH)}
t_{oh(SSCLKH–EAIV)}
t_{osu(ADSV–SSCLKH)}
t_{oh(SSCLKH–ADSV)}
t_{osu(OEV–SSCLKH)}
t_{oh(SSCLKH–OEV)}
t_{osu(EDV–SSCLKH)}
t_{oh(SSCLKH–EDIV)}
t_{osu(WEV–SSCLKH)}
t_{oh(SSCLKH–WEV)}
PARAMETER
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
MIN
0.5P – 1.5
0.5P – 2.5
0.5P – 1.6
0.5P – 2.5
0.5P – 1.7
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. For CLKMODE x1,
0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for
all output hold times.
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
1
3
BE1
5
A1
9
11
2
4
BE2 BE3 BE4
6
A2 A3
A4
8
7
Q1
Q2
Q3
Q4
10
12
Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)
34
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