SMJ320C6701-SP Datasheet, PDF (41/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
HOLD/HOLDA TIMING
Timing Requirements for the Hold/Hold Acknowledge Cycles⁽¹⁾
(see Figure 24)
NO.
1
2
t_{su(HOLDH–CKO1H)}
t_{h(CKO1H–HOLDL)}
Setup time, HOLD high before CLKOUT1 high
Hold time, HOLD low after CLKOUT1 high
MIN
5
2
MAX
UNIT
ns
ns
(1) HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the
next cycle. Thus, HOLD can be an asynchronous input.
Switching Characteristics for the Hold/Hold Acknowledge Cycles⁽¹⁾
(seeFigure 24)
NO.
3
4
5
6
7
8
9
t_{R(HOLDL–EMHZ)}
t_{R(EMHZ–HOLDAL)}
t_{R(HOLDH–HOLDAH)}
t_{d(CKO1H–HOLDAL)}
t_{d(CKO1H–BHZ)}
t_{d(CKO1H–BLZ)}
t_{R(HOLDH–BLZ)}
PARAMETER
Response time, HOLD low to EMIF high impedance
Response time, EMIF high impedance to HOLDA low
Response time, HOLD high to HOLDA high
Delay time, CLKOUT1 high to HOLDA valid
Delay time, CLKOUT1 high to EMIF Bus high impedance⁽³⁾
Delay time, CLKOUT1 high to EMIF Bus low impedance⁽³⁾
Response time, HOLD high to EMIF Bus low impedance⁽³⁾
MIN
4P
4P
1
1 ⁽⁴⁾
1 ⁽⁴⁾
3P
MAX
2P
7P
8
8 ⁽⁴⁾
12 ⁽⁴⁾
6P
UNIT
(2)_ns
ns
ns
ns
ns
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or
write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are
occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
(3) EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and
SDWE.
(4) This parameter is not tested.
DSP Owns Bus
External Requester
DSP Owns Bus
CLKOUT1
HOLD
4
3
2
1
6
5
9
2
1
6
HOLDA
7
EMIF Bus⁽¹⁾
’C6701
Ext Req
8
’C6701
(1) EMIF bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10,
SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
Copyright © 2000–2009, Texas Instruments Incorporated
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