SMJ320C6701-SP Datasheet, PDF (48/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
SGUS030E – APRIL 2000 – REVISED JULY 2009 ............................................................................................................................................................ www.ti.com
MULTICHANNEL BUFFERED SERIAL PORT TIMING
Timing Requirements for McBSP⁽¹⁾⁽²⁾
(see Figure 31)
NO.
2
3
5
t_c(CKRX)
t_w(CKRX)
t_{su(FRH–CKRL)}
6
t_{h(CKRL–FRH)}
7
t_{su(DRV–CKRL)}
8
t_{h(CKRL–DRV)}
10
t_{su(FXH–CKXL)}
11
t_{h(CKXL–FXH)}
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
MIN
2P ⁽³⁾
P – 1⁽³⁾
13 ⁽³⁾
4
7 ⁽³⁾
4
10
1
4
4
13 ⁽³⁾
4
7 ⁽³⁾
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
(3) This parameter is not tested.
48
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