SMJ320C6701-SP Datasheet, PDF (35/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
1
2
3
BE1
4
BE2
BE3
BE4
5
A1
6
A2
A3
A4
13
14
D1
D2
D3
D4
9
10
15
16
Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)
Timing Requirements for Synchronous-Burst SRAM Cycles (Half-Rate SSCLK)
(seeFigure 16)
NO.
7
8
t_{su(EDV–SSCLKH)}
t_{h(SSCLKH–EDV)}
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
MIN
3.8
1.5
MAX
UNIT
ns
ns
Switching Characteristics for Synchronous-Burst SRAM Cycles⁽¹⁾ (Half-Rate SSCLK)
(see Figure 16 and Figure 17)
NO.
1
2
3
4
5
6
9
10
11
12
13
14
15
16
t_{osu(CEV–SSCLKH)}
t_{oh(SSCLKH–CEV)}
t_{osu(BEV–SSCLKH)}
t_{oh(SSCLKH–BEIV)}
t_{osu(EAV–SSCLKH)}
t_{oh(SSCLKH–EAIV)}
t_{osu(ADSV–SSCLKH)}
t_{oh(SSCLKH–ADSV)}
t_{osu(OEV–SSCLKH)}
t_{oh(SSCLKH–OEV)}
t_{osu(EDV–SSCLKH)}
t_{oh(SSCLKH–EDIV)}
t_{osu(WEV–SSCLKH)}
t_{oh(SSCLKH–WEV)}
PARAMETER
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
MIN
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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