SMJ320C6701-SP Datasheet, PDF (51/60 Pages) Texas Instruments – RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP
www.ti.com ............................................................................................................................................................ SGUS030E – APRIL 2000 – REVISED JULY 2009
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾
(seeFigure 33)
NO.
4
5
t_{su(DRV–CKXL)}
t_{h(CKXL–DRV)}
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
MASTER
MIN
MAX
12
4
SLAVE
MIN
MAX
2 – 3P
5 + 6P
UNIT
ns
ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP=0⁽¹⁾⁽²⁾
(see Figure 33)
NO.
1
t_{h(CKXL–FXL)}
2
t_{d(FXL–CKXH)}
3
t_{d(CKXH–DXV)}
6
t_{dis(CKXL–DXHZ)}
7
t_{dis(FXH–DXHZ)}
8
t_{d(FXL–DXV)}
PARAMETER
Hold time, FSX low after CLKX low⁽⁴⁾
Delay time, FSX low to CLKX high⁽⁵⁾
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last
data＝bit from CLKX low
Disable time, DX high impedance following last
data＝bit from FSX high
Delay time, FSX low to DX valid
MASTER ⁽³⁾
MIN
MAX
T–4
T+4
L–4
L+4
–4
4
L – 2⁽⁶⁾ L + 3⁽⁶⁾
SLAVE
MIN
MAX
3P + 1 5P + 17
UNIT
ns
ns
ns
ns
P + 4⁽⁶⁾ 3P + 17⁽⁶⁾
ns
2P + 1 4P + 13 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
(6) This parameter is not tested.
CLKX
1
2
FSX
7
6
DX
Bit 0
DR
Bit 0
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Timing Requirements SPI Master or Slave: CLKSTP = 11b, CLKXP = 0⁽¹⁾⁽¹⁾
(see Figure 34)
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
Copyright © 2000–2009, Texas Instruments Incorporated
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