DS125MB203_15 Datasheet, PDF (7/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

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DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
See ^{(1) (2) (3)}.
Supply voltage (VDD – 2.5-V mode)
Supply voltage (VIN – 3.3-V mode)
LVCMOS input / output voltage
CML input voltage
CML input current
Junction temperature
Lead temperature
Soldering (4 sec.)⁽³⁾
Storage temperature, T_stg
MIN
MAX
UNIT
–0.5
2.75
V
–0.5
4
V
–0.5
4
V
–0.5
(VDD + 0.5)
V
–30
30
mA
125
°C
260
°C
–40
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For soldering information see Absolute Maximum Ratings for Soldering, SNOA549
7.2 ESD Ratings
V_(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101,
all pins⁽²⁾
VALUE
±3000
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
7.3 Recommended Operating Conditions
Supply voltage
2.5-V mode
3.3-V mode
Ambient temperature
SMBus (SDA, SCL)
Supply noise up to 50 MHz⁽¹⁾
(1) Allowed supply noise (mVp-p sine wave) under typical conditions.
MIN
2.375
3.0
–40
NOM
2.5
3.3
25
MAX
2.625
3.6
85
3.6
100
UNIT
V
V
°C
V
mVp-p
7.4 Thermal Information
THERMAL METRIC⁽¹⁾
DS125MB203
NYJ (WQFN)
UNIT
54 PINS
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance, No Airflow, 4 layer JEDEC
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
26.6
°C/W
10.8
°C/W
4.4
°C/W
0.2
°C/W
4.3
°C/W
1.5
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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