DS125MB203_15 Datasheet, PDF (43/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

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DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
Power Supply Bypassing (continued)
For 3.3-V mode of operation, use the following steps:
1. Tie VDD_SEL = 0 with 1-kΩ resistor to GND.
2. Feed 3.3-V supply into VIN pin. Local 1.0-μF decoupling at VIN is recommended.
3. See information on VDD bypass below.
4. SDA and SCL pins should connect pullup resistor to VIN
5. Any 4-Level input which requires a connection to Logic 1 should use a 1-kΩ resistor to VIN
For 2.5-V mode of operation, use the following steps:
1. VDD_SEL = Float
2. VIN = Float
3. Feed 2.5-V supply into VDD pins.
4. See information on VDD bypass below.
5. SDA and SCL pins connect pullup resistor to VDD for 2.5-V uC SMBus IO
6. SDA and SCL pins connect pullup resistor to VDD for 3.3-V uC SMBus IO
7. Any 4-Level input which requires a connection to Logic 1 should use a 1-kΩ resistor to VDD
3.3 V mode
2.5 V mode
Enable
VDD_SEL
Internal
voltage
regulator
2.5 V
VIN
VDD
VDD
VDD
3.3 V
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
0.1 µF
0.1 µF
0.1 µF
Disable
VDD_SEL
open
Internal
voltage
regulator
VIN
open
VDD
0.1 µF
2.5 V
VDD
VDD
0.1 µF
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
0.1 µF
VDD
0.1 µF
VDD
0.1 µF
VDD
0.1 µF
VDD
0.1 µF
Place 0.1 µF close to VDD Pin
Total capacitance should be 7 0.5 µF
Place capacitors close to VDD Pin
Figure 15. 3.3-V or 2.5-V Supply Connection Diagram
Two approaches are recommended to ensure that the DS125MB203 is provided with an adequate power supply
bypass. First, the supply ( V_DD) and ground (GND) pins should be connected to power planes routed on adjacent
layers of the printed-circuit-board. Second, pay careful attention to supply bypassing through the proper use of
bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each V_DD pin such that the
capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the
parasitic inductance of the capacitor and also help in placement close to the V_DD pin. If possible, the layer
thickness of the dielectric should be minimized so that the V_DD and GND planes create a low inductance supply
with distributed capacitance.
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