DS125MB203_15 Datasheet, PDF (42/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
Typical Application (continued)
9.2.3 Application Curves
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Figure 11. TL = 10-inch 5–mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = 0, F = 02'h, DEM[1:0] = 0, 1
Figure 12. TL = 20-inch 5–mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = 0, 1
Figure 13. TL = 30-inch 5–mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1
Figure 14. TL1 = 20-inch 5–mil FR4 Trace, TL2 = 10-inch
5–mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = R, 1 = 03'h, DEM[1:0] = R, 0
10 Power Supply Recommendations
10.1 Power Supply Bypassing
The DS125MB203 has an optional internal voltage regulator to provide the 2.5-V supply to the device. In 3.3-V
mode, the VIN pin = 3.3 V is used to supply power to the device and the VDD pins should be left open. The
internal regulator will provide the 2.5 V to the VDD pins of the device and a 0.1-μF capacitor is needed at each of
the five VDD pins for power supply de-coupling (total capacitance should be ≤ 0.5 μF), and the VDD pins should
be left open. The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5-V mode, the VIN pin
should be left open and 2.5-V supply must be applied to the VDD pins. The VDD_SEL pin must be left open (no
connect) to disable the internal regulator.
The DS12500MB203 can be configured for 2.5-V operation or 3.3-V operation. The lists below outline required
connections for each supply selection.
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