DS125MB203_15 Datasheet, PDF (34/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
www.ti.com
Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
BIT
FIELD
TYPE DEFAULT
EEPROM
REG BIT
DESCRIPTION
7:6
SEL1 Control
Select for lane 1.
00: 0 - Selects input S_INB1±, output S_OUTB1±.
01: 20kΩ to GND - Selects input S_INB1±, output S_OUTA1±
10: FLOAT - Selects input S_INA1±, output S_OUTB1±
11: 1 - Selects input S_INA1±, output S_OUTA1±.
0x5F
5:4
Control SEL[1:0] and
INPUT_EN
SEL0 Control
R/W
0x00
3:2 INPUT_EN Control
Select for lane 0.
00: 0 - Selects input S_INB0±, output S_OUTB0±.
01: 20 kΩ to GND - Selects input S_INB0±, output S_OUTA0±
10: FLOAT - Selects input S_INA0±, output S_OUTB0±
11: 1 - Selects input S_INA0±, output S_OUTA0±.
00: 0 - Normal Operation, FANOUT is disabled, use SEL0/1 to select the A
or B input/output (see SEL0/1 pin), input always enabled with 50 Ohms.
01: 20 kΩ to GND - Reserved
10: FLOAT - AUTO - Use RX Detect, SEL0/1 to determine which input or
output to enable, FANOUT is disable.
11: 1 - Normal Operation, FANOUT is enabled (both S_OUT0/1 are ON).
Input always enabled with 50 Ohms.
1:0
Reserved
1: Block INPUT_EN pin control; use Reg_5F to configure.
0: Allow INPUT_EN pin control
34
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