DS125MB203_15 Datasheet, PDF (10/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
Electrical Characteristics (continued)
See ⁽¹⁾⁽²⁾.
PARAMETER
TEST CONDITIONS
DJE5
Residual deterministic 8 meters 30 awg cable, VID = 0.6 Vp-p, PRBS15,
jitter at 8 Gbps
EQ = 0F'h, DEM = 0 dB
DE-EMPHASIS (MODE = 0)
DJD1
Residual deterministic
jitter at 12 Gbps
Input channel: 20-inch 5-mils FR4, Output channel:
10-inch 5-mils FR4, VID = 0.6 Vp-p, PRBS15,
EQ = 03'h, VOD = 1.0 Vp-p, DEM = −3.5 dB
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MIN TYP MAX UNIT
0.33
UI
0.1
UI
7.6 Electrical Characteristics – Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL
Data, clock input low voltage
V_IH
Data, clock input high voltage
2.1
I_PULLUP
Current through pullup resistor or
current source
High power specification
4
V_DD
I_LEAK-Bus
I_LEAK-Pin
C_I
R_TERM
Nominal bus voltage
Input leakage per bus segment
Input leakage per device pin
Capacitance for SDA and SCL
External termination resistance pull
to V_DD = 2.5 V ± 5% OR 3.3 V ±
10%
See ⁽¹⁾
See ^{(1) (2)}
Pullup V_DD = 3.3 V^(1)(2)(3)
Pullup V_DD = 2.5 V^(1)(2)(3)
2.375
–200
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
TYP
–15
2000
1000
MAX UNIT
0.8
V
3.6
V
mA
3.6
V
200 µA
µA
10
pF
Ω
Ω
7.7 Timing Requirements – Serial Bus Interface
FSMB
TBUF
THD:STA
TSU:STA
TSU:STO
THD:DAT
TSU:DAT
T_LOW
T_HIGH
t_F
t_R
t_POR
Bus operating Frequency
ENSMB = VDD (slave mode)
ENSMB = FLOAT (master mode)
Bus free time between stop and start condition
Hold time after (repeated)
start condition. After this
period, the first clock is
generated.
At I_PULLUP, maximum
Repeated start condition set-up time
Stop condition set-up time
Data hold time
Data set-up time
Clock low period
Clock high period
Clock / data fall time
See ⁽¹⁾
Clock / data rise time
Time in which a device
must be operational after
power-on reset
See ^{(1) (2)}
MIN
NOM
MAX UNIT
400 kHz
280
400
520 kHz
1.3
µs
0.6
µs
0.6
µs
0.6
µs
0
ns
100
ns
1.3
µs
0.6
50
µs
300
ns
300
ns
500
ms
(1) Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(2) Specified by Design. Parameter not tested in production.
10
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