DS125MB203_15 Datasheet, PDF (6/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
www.ti.com
Pin Functions: Pin Control
NAME
PIN
NO.
TYPE
DESCRIPTION
ENSMB = 0 (PIN MODE)
EQ_D0,
EQ_D1
EQ_S0,
EQ_S1
20, 19, 46,
47
I, 4-LEVEL,
LVCMOS
EQ_D[1:0] and EQ_S[1:0] control the level of equalization on the high-speed input pins. The
inputs are organized into two sides. The D side is controlled with the EQ_D[1:0] pins and the
S side is controlled with the EQ_S[1:0] pins. See Table 2.
DEM_S0,
DEM_S1
DEM_D0,
DEM_D1
49, 50, 53,
54
I, 4-LEVEL,
LVCMOS
DEM_D[1:0] and DEM_S[1:0] control the level of VOD and de-emphasis on the high-speed
output. The outputs are organized into two sides. The D side is controlled with the
DEM_D[1:0] pins and the S side is controlled with the DEM_S[1:0] pins. See Table 3.
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
MODE
21
I, 4-LEVEL,
LVCMOS
0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
INPUT_EN
0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see
SEL0/1 pin), input always enabled with 50 Ω.
22
I, 4-LEVEL,
LVCMOS
20 kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable,
FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled
with 50 Ω.
SEL0
Select pin for lane 0.
23
I, 4-LEVEL,
LVCMOS
0: Selects input S_INB0±, output S_OUTB0±.
20 kΩ to GND: Selects input S_INB0±, output S_OUTA0±.
FLOAT: Selects input S_INA0±, output S_OUTB0±.
1: Selects input S_INA0±, output S_OUTA0±.
SEL1
Select pin for lane 1.
26
I, 4-LEVEL,
LVCMOS
0: Selects input S_INB1±, output S_OUTB1±.
20 kΩ to GND: Selects input S_INB1±, output S_OUTA1±.
FLOAT: Selects input S_INA1±, output S_OUTB1±.
1: Selects input S_INA1±, output S_OUTA1±.
6
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