DS125MB203_15 Datasheet, PDF (14/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
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8.3 Feature Description
8.3.1 4-Level Input Configuration Guidelines
The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
LEVEL
0
R
F
1
SETTING
Tie 1 kΩ to GND
Tie 20 kΩ to GND
Float (leave pin open)
Tie 1 kΩ to V_IN or V_DD
RESULTING PIN VOLTAGE
3.3-V MODE
2.5-V MODE
0.1 V
0.08 V
1/3 × V_IN
2/3 × V_IN
V_IN – 0.05 V
1/3 × V_DD
2/3 × V_DD
V_DD – 0.04 V
The typical 4-Level Input thresholds are as follows:
• Internal Threshold between 0 and R = 0.2 × V_IN or V_DD
• Internal Threshold between R and F = 0.5 × V_IN or V_DD
• Internal Threshold between F and 1 = 0.8 × V_IN or V_DD
To minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and pulldown
resistors are recommended. If several four level inputs require the same setting, it is possible to combine two or
more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single 500-Ω
resistor is a valid way to save board space.
8.4 Device Functional Modes
8.4.1 Pin Control Mode
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per Table 3. The receiver electrical idle detect threshold is also adjustable through the SD_TH pin.
8.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the
SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting
when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-emphasis levels are
set by registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
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