DS125MB203_15 Datasheet, PDF (21/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

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ADDRESS
REGISTER
NAME
BIT
7
0x00
6:3
Observation
2
1
0
0x01
PWDN Channels
7:0
0x02
0x03
0x04
0x05
0x06
7
6
Override RESET
5:2
Control
1
0
Reserved
7:0
Reserved
7:0
Reserved
7:0
7:5
4
Slave Register Control
3
2:0
DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
Table 7. SMBUS Slave Mode Register Map
FIELD
Reserved
Address Bit
AD[3:0]
EEPROM Read
Done
Block Reset
Reset
PWDN CHx
Reserved
Reserved
Reserved
Reserved
Override RESET
Reserved
Reserved
Reserved
Reserved
Reserved
Register Enable
Reserved
TYPE DEFAULT
R/W
R
0x00
R
R/W
R/W
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x10
EEPROM
REG BIT
Yes
Yes
Yes
Yes
Yes
DESCRIPTION
Set bit to 0
Observation of AD[3:0] bits
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
1 = Device completed the read from external EEPROM
1: Block bit 0 from resetting the registers; self clearing.
SMBus Reset
1: Reset registers to default value; self clearing.
Power Down per Channel
[7]: CH7 (NC – S_OUTB1)
[6]: CH6 (D_IN1 – S_OUTA1)
[5]: CH5 (NC – S_OUTB0)
[4]: CH4 (D_IN0 – S_OUTA0)
[3]: CH3 (D_OUT1 – S_INB1)
[2]: CH2 (NC – S_INA1)
[1]: CH1 (D_OUT0 – S_INB0)
[0]: CH0 (NC – S_INA0)
0x00 = all channels enabled
0xFF = all channels disabled
Note: Override PWDN pin and enable register control through Reg 0x02[0]
Set bit to 0
Set bit to 0
Set bits to 0
Set bit to 0
1: Block RESET pin control; use Reg_01 to configure.
0: Allow RESET pin control.
Set bits to 0
Set bits to 0
Reserved
Set bits to 0
Set bit to 1
1 = Enable SMBus slave mode register control
0 = Disable SMBus register control
Note: To change VOD, DEM, and EQ of the channels in slave mode, this
bit must be set to 1.
Set bits to 0
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