DS125MB203_15 Datasheet, PDF (4/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
www.ti.com
Pin Functions: Common Connections⁽¹⁾
PIN
NAME
NO.
TYPE
DESCRIPTION
DIFFERENTIAL HIGH-SPEED INPUTS AND OUTPUTS
D_IN0+,
D_IN0-,
D_IN1+,
D_IN1-
10, 11, 15, 16
Inverting and noninverting CML differential inputs to the equalizer. A gated on-chip 50-
I
Ω termination resistor connects D_INn+ to VDD and D_INn– to VDD when enabled. AC
coupling required on high-speed I/O.
D_OUT0+, D_
OUT0-,
D_OUT1+,
D_OUT1-
3, 4, 7, 8
Inverting and noninverting low power differential signaling 50-Ω outputs with de-
O
emphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on
high-speed I/O.
S_INA0+,
S_INA0-,
S_INA1+,
S_INA1-
45, 44, 40, 39
Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω
I
termination resistor connects S_INAn+ to VDD and S_INAn– to VDD. AC coupling
required on high-speed I/O.
S_INB0+,
S_INB0-,
S_INB1+,
S_INB1-
43, 42, 38, 37
Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω
I
termination resistor connects S_INBn+ to VDD and S_INBn– to VDD. AC coupling
required on high-speed I/O.
S_OUTA0+,
S_OUTA0-,
S_OUTA1+,
S_OUTA1-
35, 34, 31, 30
Inverting and noninverting low power differential signaling 50-Ω outputs with de-
O
emphasis. Fully compatible with AC-coupled CML inputs.
S_OUTB0+,
S_OUTB0-,
S_OUTB1+,
S_OUTB1-
33, 32, 29, 28
Inverting and noninverting low power differential signaling 50-Ω outputs with de-
O
emphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on
high-speed I/O.
CONTROL PINS - SHARED (LVCMOS)
ENSMB
System Management Bus (SMBus) enable pin
48
I, FLOAT,
LVCMOS
Tie 1 kΩ to VDD = register access SMBus slave mode
FLOAT = Read external EEPROM (master SMBUS mode)
Tie 1 kΩ to GND = pin mode
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
RESET
52
I, LVCMOS
0: Normal operation (device is enabled).
1: Low power mode.
VDD_SEL
Controls the internal regulator
25
I, FLOAT FLOAT: 2.5-V mode
Tied to GND: 3.3-V mode
POWER
GND
DAP
Power
Ground pad (DAP - die attach pad).
VDD
9, 14,36, 41,
51
Power
Power supply pins CML/analog
2.5-V mode, connect to 2.5V ±5%
3.3-V mode, connect 0.1-µF cap to each VDD pin
VIN
24
Power
In 3.3-V mode, feed 3.3 V ±10% to VIN
In 2.5-V mode, leave floating.
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
4
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS125MB203