DS125MB203_15 Datasheet, PDF (40/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 General Recommendations
The DS125MB203 is a high-performance circuit capable of delivering excellent performance. Pay careful
attention to the details associated with high-speed design as well as providing a clean power supply. Refer to the
information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high speed
design tips to address signal integrity design issues.
Pattern
Generator
VID = 1.0 Vp-p,
DE = 0 dB
PRBS15
TL
Lossy Channel
IN DS125MB203 OUT
Scope
BW = 60 GHz
Figure 8. Test Set-Up Connections Diagram
Pattern
Generator
VID = 1.0 Vp-p,
DE = 0 dB
PRBS15
TL1
Lossy Channel
IN DS125MB203 OUT
TL2
Lossy Channel
Figure 9. Test Set-Up Connections Diagram
Scope
BW = 60 GHz
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