DS125MB203_15 Datasheet, PDF (26/54 Pages) Texas Instruments – Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer

DS125MB203
SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015
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ADDRESS
REGISTER
NAME
0x26
CH3
D_OUT1 – S_INB1
DEM
0x27
CH3
D_OUT1 – S_INB1
Reserved
0x28
Signal Detect Status
Control
0x29-0x2A
Reserved
Table 7. SMBUS Slave Mode Register Map (continued)
BIT
FIELD
TYPE DEFAULT
7
RXDET Status
R
6:5
Reserved
4:3
Reserved
0x02
R/W
2:0
DEM Control
7
Reserved
6:4
Reserved
R/W
3:2
Reserved
1:0
Reserved
7
Reserved
6
Reserved
5:4 High SD_TH Status
R/W
3:2
Fast Signal Detect
Status
0x00
0x0C
1:0
Reduced SD Status
Gain
7:0
Reserved
R/W
0x00
EEPROM
REG BIT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DESCRIPTION
Observation bit for RXDET CH3 - CHB_3
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
Set bits to 0
Set bits to 0
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Set bit to 0
Set bits to 0
Set bits to 0
Set bits to 0
Set bit to 0
Set bit to 0
Enable higher range of signal detect status thresholds
[5]: CH0 - CH3
[4]: CH4 - CH7
Enable fast signal detect status
[3]: CH0 - CH3
[2]: CH4 - CH7
Note: In fast signal detect, assert/deassert response occurs after
approximately 3-4 ns
Enable Reduced Signal Detect Status Gain
[1]: CH0 - CH3
[0]: CH4 - CH7
Set bits to 0
26
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