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| TLC34076_16 Datasheet, PDF (68/69 Pages) Texas Instruments – Video Interface Palette | |||
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Mechanical Data (continued)
GA-GB (S-CPGA-P12 X 12)
CERAMIC PIN GRID ARRAY PACKAGE
A or A1 SQ
1.100 (27,94) TYP
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12
0.050 (1,27) DIA
4 Places
0.022 (0,55)
DIA TYP
0.016 (0,41)
B or B1
C or C1
0.140 (3,56)
0.120 (3,05)
0.100 (2,54)
DIM
MIN
MAX
Notes
A
1.240 (31,50)
A1 1.180 (29,97)
B
0.110 (2,79)
B1 0.095 (2,41)
C
0.040 (1,02)
C1 0.025 (0,63)
1.280 (32,51)
1.235 (31,37)
0.205 (5,21)
0.205 (5,21)
0.060 (1,52)
0.060 (1,52)
Large
Outline
Small
Outline
Cavity
Up
Cavity
Down
Cavity
Up
Cavity
Down
MAXIMUM PINS WITHIN MATRIX â 144
4040114-5 / B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending on package vendor.
D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material
condition and within 0.015 (0,38) radius relative to the center of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Falls within MIL-STD-1835 CMGA4-PN and CMGA16-PN and JEDEC MO-067AD and MO-066AD,
respectively
Dâ2
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