TLC34076_16 Datasheet, PDF (18/69 Pages) Texas Instruments – Video Interface Palette

2.2.1 Writing to the Color Palette RAM
To load the color palette RAM, the MPU must first write to the address register (write mode) with the address
where the modification is to start. This action is followed by three successive writes to the palette-holding
register with eight bits each of red, green, and blue data. After the blue data write cycle, the three bytes of
color are concatenated into a 24-bit word and written to the color palette RAM location specified by the
address register. The address register then increments to point to the next color palette RAM location, which
the MPU may modify by simply writing another sequence of red, green, and blue data bytes. A block of color
values in consecutive locations may be written to by writing the start address and performing continuous
red, green, and blue write cycles until the entire block has been written.
2.2.2 Reading From the Color Palette RAM
Reading from the color palette RAM is performed by writing the location to be read to the address register.
This action initiates a transfer from the color palette RAM into the holding register followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (6 or 8 bits, depending on the 8/6 mode) for the specified location. Following the blue read cycle,
the contents of the color palette RAM at the address specified by the address register are copied into the
holding register and the address register is again incremented. As with writing to the color palette RAM, a
block of color values in consecutive locations may be read by writing the start address and performing
continuous red, green, and blue read cycles until the entire block has been read.
2.2.3 Palette Page Register
The 8-bit palette page register provides high-speed color changing by removing the need for color palette
RAM reloading. When using 1, 2, or 4 bit-planes, the additional planes are provided by the palette page
register; e.g., when using four bit-planes, the pixel inputs specify the lower four bits of the color palette RAM
address with the upper four bits being specified by the palette register. This provides the capability of
selecting from 16 palette pages with only one chip access, thus allowing all the screen colors to be changed
at the line frequency. A bit-to-bit correspondence is used; therefore, in the above configuration, palette page
register bits 7 – 4 map onto color palette RAM address bits 7 – 4 respectively. This is listed in Table 2–2.
Since there is only one bit of overlay data in the 5-5-5 true color modes, the page register fills the seven
remaining MSBs (same as one bit-plane in Table 2–2). All 8 bits need to be cleared to 0 in order to enable
true color.
The additional bits from the palette page register are inserted before the read mask and hence, are subject
to masking.
Table 2–2. Allocation of Palette Page Register Bits
NUMBER OF
COLOR PALETTE RAM ADDRESS BITS
BIT PLANES _MSB
LSB
8
MMMMMMMM
4
P7 P6 P5 P4 M M M M
2
P7 P6 P5 P4 P3 P2 M M
1
P7 P6 P5 P4 P3 P2 P1 M
Pn = nth bit from palette page register
M = bit from pixel port
2.3 Input/Output Clock Selection and Generation
The TLC34076 provides a maximum of five clock inputs. Three are dedicated to TTL inputs; the other two
can be selected as either one ECL input or two extra TTL inputs. The TTL and ECL inputs can be used for
video rates up to 135 MHz. The dual-mode clock input (ECL/TTL) is primarily an ECL input but can be used
2–2