TLC34076_16 Datasheet, PDF (24/69 Pages) Texas Instruments – Video Interface Palette

VCLK
BLANK
at Input Terminal
SFLAG/NFLAG
Load
(Internal Signal
for Data Latch)
Blank
(Internal Signal
Before DOTCLK
Pipeline Delay)
Pixel Data
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Last
Group
3rd
5th
2nd Group 4th _Group 6th
Group
Group
Group
1st Group of Pixel Data
SCLK Between Split Shift-Register
and Regular Shift Register Transfer
NOTE A: Either the SSRT function is disabled (general-control register bit 2 = 0), or the SFLAG/NFLAG input is held
low when the SSRT function is enabled (general-control register bit 2 = 1).
Figure 2–5. SCLK/VCLK Control Timing (SSRT Enabled,
SCLK Frequency = 4 × VCLK Frequency)
2.4 Multiplexing Scheme
The TLC34076 offers a highly versatile multiplexing scheme as illustrated in Table 2–6. The on-chip
multiplexing allows the system to be reconfigured to the amount of RAM available. For example, when only
256K bytes of memory are available, an 800-by-600 resolution mode with four bit-planes (4 bits per pixel)
can be implemented using an 8-bit wide pixel bus. If, at a later date, another 256K bytes are added to another
8 bits of the pixel bus, the user has the option of using eight bit-planes at the same resolution or four
bit-planes at a 1024 × 768 resolution. When an additional 512K bytes are added to the remaining 16 bits
of the pixel bus, the user has the option of eight bit-planes at 1024 × 768 resolution or four bit-planes at
1280 × 1024 resolution. All the above can be achieved without any hardware modification and without any
increase in the speed of the pixel bus.
2–8