TLC34076_16 Datasheet, PDF (27/69 Pages) Texas Instruments – Video Interface Palette

MODE
Table 2–6. Mode and Bus Width Selection (Continued)
MUX CONTROL REGISTER BITS^†
5
4
3
2
1
0
DATA BITS
PER
PIXEL BUS
PIXEL^‡
WIDTH
SCLK
DIVIDE
RATIO^§
0
1
1
1
1
1
4
16
4
5#
6|| See Table 2–7 and Table 2–8
PIXEL
LATCHING
SEQUENCE^¶
NFLAG = 0:
1) P3 – P0
2) P11 – P8
3) P19 – P16
4) P27 – P24
NFLAG = 1:
1) P7 – P4
2) P15 – P12
3) P23 – P20
4) P31 – P28
† _{Bits 6 and 7 are don’t care bits.}
‡ _{This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,}
often referred to as the number of bit-planes. This may be color palette address data (modes 0 – 5) or DAC data
(mode 6).
§ _{The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per}
bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8
bit-planes, 4 pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but must
be written to the output clock selection register.
¶ _{For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are}
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 3 with a 16-bit pixel bus width, the rising edge of SCLK latches all the data
groups, and the pixel clock shifts them out in the order P3 – P0, P7 – P4, P11 – P8, P15 – P12.
# _{Mode 5 is special nibble mode, the only mode in which the pixel bus width is not equal to the actual physical width, in}
bits, of the pixel bus. In this mode, the pixel bus is physically 32 bits wide; depending on the value of SFLAG/NFLAG,
either the upper or lower nibble of each of the four physical bytes is selected to comprise the 16 bits of pixel data (equal
to four 4-bit pixels).
|| _{Mode 6 is true color mode, in which 24 bits of color information are transferred directly from the pixel port to the DACs;}
overlay is implemented with the remaining eight bits of the pixel bus. The distribution of pixel port data to the DACs is
as follows: P31 – P24 are passed to the blue DAC, P23 – P16 are passed to the green DAC, and P15 – P8 are passed
to the red DAC. P7 – P0 generate overlay data; this operation can be disabled by either grounding P7 – P0 or by clearing
the read mask (see subsection 2.4.6).
NOTE 1: Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
2.4.1 VGA Pass-Through Mode
Mode 0, the VGA pass-through mode, emulates the VGA modes of most personal computers. The
advantage of this mode is that the TLC34076 can take data presented on the feature connectors of most
VGA-compatible PC systems into the device on a separate bus, thus requiring no external multiplexing. This
feature is particularly useful for systems in which the existing graphics circuitry is on the motherboard. In
this instance, it enables implementation of a drop-in graphics card that maintains compatibility with all
existing software by using the on-board VGA circuitry but routing the emerging bit-plane data through the
TLC34076. This is the default mode at power-up. When the VGA pass-through mode is selected after the
device is powered up, the clock selection register, the general control register, and the pixel read mask
register are set to their default states automatically.
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