TLC34076_16 Datasheet, PDF (54/69 Pages) Texas Instruments – Video Interface Palette

3.6 Switching Characteristics (TLC34076C and TLC34076M) Over
Recommended Ranges of Supply Voltages and Operating Temperature
(Continued)
PARAMETER
SCLK frequency (see Note 7)
VCLK frequency
ten
Enable time, RD low to D0 – D7 valid (see
Figure 3–1)
tdis
Disable time, RD high to D0 – D7 disabled (see
Figure 3–1)
Valid time, D0 – D7 valid after RD high (see
tv
Figure 3–1)
tPLH
Propagation delay, SFLAG/NFLAG high to SCLK ↑
(see Note 8 and Figure 3–3)
td1
Delay time, RD low to D0 – D7 valid (see
Figure 3–1)
Delay time, selected input clock high/low to DOTCLK
td2 _{(internal signal) high/low (see Figure 3–2)}
-135
MIN TYP^†
MAX
85
85
-170
MIN TYP^†
UNIT
MAX
85 MHz
85 MHz
40
40 ns
17
17 ns
5
5
ns
0
20
0
20 ns
5
5
ns
7
7
ns
td3
Delay time, DOTCLK high/low to VCLK high/low (see
Figure 3–2)
6
6
ns
td4
Delay time, VCLK high/low to SCLK high/low
(see Note 9 and Figure 3–2)
0
5
0
5 ns
td5
Delay time, DOTCLK high/low to SCLK high/low (see
Figure 3–2)
8
8
5 ns
† _{All typical values are at VDD = 5 V, TA = 25°C.}
NOTES: 7. SCLK can drive output capacitive loads up to 60 pF, with worst case transition time between 10% and 90%
levels less than 4 ns (typical 3 ns). SCLK can drive output capacitive loads up to 120 pF, with typical
transition time (10% to 90%) of 4 ns.
8. This parameter applies when the split shift-register transfer (SSRT) function is enabled (see subsection
2.9.1 for details).
9. VCLK frequency = SCLK frequency.
10. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
11. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
12. SCLK can be programmed to latch pixel data at the input port up to this limit. However, the SCLK output
buffer can only be used up to the SCLK frequency limit of 85 MHz.
13. Measured between 10% and 90% of the full-scale transition.
3–10