TLC34076_16 Datasheet, PDF (20/69 Pages) Texas Instruments – Video Interface Palette

Table 2–5. VCLK/SCLK Divide Ratio Selectio (Output Clock Selection Register Value in Hex)
SCLK
VCLK
BITS
2. . .0^{
000 001 010 011 100 101
BITS
5. . .3^{
divide
DOTCLK
1
2
4
8
16
32
by
000
1
00
01
02
03
04
05
001
2
08
09
0A
0B
0C
0D
010
4
10
11
12
13
14
15
011
8
18
19
1A
1B
1C
1D
100
16
20
21
22
23
24
25
101
32
28
29
2A
2B
2C
2D
† _{Output clock selection register bits}
The ECL input can be used as a differential or single-ended input. When the CLK3 input is used as a
single-ended ECL input, CLK3 must be externally terminated to set the input common-mode signal level.
This can be done with a simple resistor divider, as is the case with fully differential ECL.
SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals like
BLANK and SYNC. While SCLK and VCLK are designed as a general-purpose shift clock and video clock,
respectively, they also interface directly with the TMS340x0 graphics signal processor (GSP) family directly.
Even though SCLK and VCLK can be selected independently, there is still a relationship between the two
as discussed in subsequent paragraphs. Many system considerations have been carefully covered in the
design, leaving maximum freedom to the user.
Internally, both SCLK and VCLK are generated from a common clock counter that increments on the rising
edge of the DOTCLK. Therefore, when VCLK is enabled, it is in phase with SCLK (see Figure 2–1).
DOTCLK
VCLK
(DOTCLK/4
as an example)
SCLK
(DOTCLK/2
as an example)
Figure 2–1. DOTCLK/VCLK/SCLK Relationship
The internal clock counter is reset to 0 any time the output clock-selection register (bits 5, 4, 2, 1) are all set
to 1. This provides a simple mechanism to synchronize multiple VIPs, by providing a known phase
relationship for the various system clocks. One can write directly to the Output Clock Selection register to
cause this to occur, or any of the various resets (for POR, hardware, and software, see Section 1.5) also
causes the appropriate bits to be written and the counters to reset. It is up to the user to provide some means
of disabling the dot-clock input to the part while this reset is occurring, when multiple parts are to be
synchronized.
Appendix A discusses the SCLK/VCLK relationship specific to the TMS340x0 GSP.
2–4