TLC34076_16 Datasheet, PDF (53/69 Pages) Texas Instruments – Video Interface Palette

3.6 Switching Characteristics for TLC34076C and TLC34076M Over
Recommended Ranges of Supply Voltages and Operating Temperature
PARAMETER
SCLK frequency (see Note 7)
VCLK frequency
ten
Enable time, RD low to D0 – D7 valid (see
Figure 3–1)
-85
MIN TYP^† MAX
85
85
-110
MIN TYP^†
MAX
85
85
UNIT
MHz
MHz
40
40 ns
tdis
Disable time, RD high to D0 – D7 disabled (see
Figure 3–1)
17
17 ns
tv
Valid time, D0 – D7 valid after RD high (see
Figure 3–1)
5
5
ns
tPLH
Propagation delay, SFLAG/NFLAG high to SCLK↑
(see Note 8 and Figure 3–3)
0
20
0
20 ns
td1
Delay time, RD low to D0 – D7 starting to turn on
(see Figure 3–1)
5
5
ns
td2
Delay time, selected input clock high/low to
DOTCLK (internal signal) high/low (see Figure 3–2)
7
7
ns
Delay time, DOTCLK high/low to VCLK high/low
td3 _{(see Figure 3–2)}
6
6
ns
td4
Delay time, VCLK high/low to SCLK high/low (see
Note 9 and Figure 3–2)
0
5
0
5 ns
td5
Delay time, DOTCLK high/low to SCLK high/low
(see Figure 3–2)
8
8
ns
Delay time, DOTCLK high to IOR/IOG/IOB active
td6 (analog output delay time) (see Note 10 and
20
Figure 3–2)
20
ns
td7
Analog output settling time (see Note 11 and
Figure 3–2)
8
6 ns
td8
Delay time, DOTCLK high to HSYNCOUT and
VSYNCOUT valid (see Figure 3–2)
5
3
ns
tw6
Pulse duration, SCLK high (see Note 12 and
Figure 3–3)
15
55 15
55 ns
tr
Rise time at HSYNCOUT analog output
(see Note 13 and Figure 3–2)
2
2
ns
Analog output skew
0
2
0
2 ns
† _{All typical values are at VDD = 5 V, TA = 25°C.}
NOTES: 7. SCLK can drive an output capacitive load up to 60 pF with worst-case transition time between the 10% and
90% levels less than 4 ns (typical 3 ns). SCLK can drive output capacitive loads up to 120 pF, with typical
transition time (10% to 90%) of 4 ns.
8. This parameter applies when the split shift-register transfer (SSRT) function is enabled (see subsection
2.9.1 for details).
9. VCLK frequency = SCLK frequency.
10. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
11. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
12. SCLK can be programmed to latch pixel data at the input port up to this limit. However, the SCLK output
buffer can only be used up to the SCLK frequency limit of 85 MHz.
13. Measured between 10% and 90% of the full-scale transition.
3–9