TLC34076_16 Datasheet, PDF (37/69 Pages) Texas Instruments – Video Interface Palette

When the SSRT function is enabled but SFLAG/NFLAG is held low, SCLK runs as if the SSRT function is
disabled. The SFLAG/NFLAG input is not qualified by the BLANK signal and needs to be held low whenever
an SSRT SCLK pulse is not desired (see subsection 2.3.1 and Figures 2–2 through 2– 8 for more system
details).
2.9.2 Special Nibble Mode
Special nibble mode is enabled when the SNM bit (bit 3 in the General Control register) is set to 1 and the
SSRT bit (bit 2 in the general control register) is reset to 0 (see Section 2.11). The special nibble mode
provides a variation of the 4-bit pixel mode with a 16-bit bus width. While all 32 inputs (P0 – P31) are
connected as four bytes, the 16-bit data bus is composed of the lower or upper nibble of each of the four
bytes, depending on the level of the SFLAG/NFLAG input. The pixel data is distributed to the 16-bit data
bus as shown in Table 2–10.
Table 2–10. Pixel Data Distribution in Special Nibble Mode
SNM BIT = 1, SSRT BIT = 0
SFLAG/NFLAG = 1
SFLAG/NFLAG = 0
P7 – P4
P15 – P12
P23 – P20
P31 – P28
P3 – P0
P11 – P8
P19 – P16
P27 – P24
The SFLAG/NFLAG value is not latched by the TLC34076; therefore, it should stay at the same level during
the whole active display period, changing levels only during the BLANK signal active time. (see to
Figure 2–10, which is similar to Figure 2–2 except that the BLANK signal timing reference to SFLAG/NFLAG
is explained). The SFLAG/NFLAG input has to meet the setup time and hold the data long enough to ensure
that no pixel data is missed.
CAUTION:
If pixel data are not held valid until both SCLK and BLANK go low, the last few
pixels can be missed.
2–21