TLC34076_16 Datasheet, PDF (15/69 Pages) Texas Instruments – Video Interface Palette

1.5 Terminal Functions (TLC34076C and TLC34076M) (Continued)
TERMINAL
I/O
NAME
NO.{
NO.}
DESCRIPTION
MUXOUT
63
M7
O _{MUX output control. MUXOUT is software programmable. It is set}
low to indicate to external devices that VGA pass-through mode is
being used when the multiplex control register value is set to 2Dh.
When bit 7 of the general-control register is set high after the mode
is set, this output goes high. This terminal is only used for external
control; it affects no internal circuitry.
P0 – P31
29 –1, A10, B9, A9, I Pixel input port. This port can be used in various modes as shown
84 – 82 B8, A8, B7,
in the MUX control register. It is recommended that unused terminals
A7, B6, A6,
be tied to ground. It also supports little-endian and big-endian data
A5, B5, A4,
formats. All the unused terminals must be tied to GND.
B4, A3, A2,
B3, B2, C3,
A1, C2, B1,
C1, D2, D1,
E2, E1, F1,
F2, G1, G2,
H1, H2
RD
31
B10
I Read strobe input. A low on RD initiates a read from the TLC34076
register map. Reads are performed asynchronously and are initiated
on the falling edge of RD (see Figure 3 –1).
RS0 – RS3
32–35 A12, C10,
B11, C11
I Register select inputs. RSx specifies the location in the register map
that is to be accessed (see Table 2–1).
SCLK
79
K1
O Shift clock output. SCLK is selected as a submultiple of the dot clock
input. SCLK is gated off during blanking.
SFLAG/
NFLAG
62
M8
I Split shift register transfer flag or nibble flag input. SFLAG/NFLAG
has two functions. When the general control register bit 3 = 0 and bit
2 = 1, the split shift register transfer function is enabled and a
low-to-high transition on SFLAG/NFLAG during a blank sequence
initiates an extra SCLK cycle to allow a split shift register transfer in
the VRAMs. When the general control register bit 3 = 1 and bit 2 = 0,
special nibble mode is enabled and this input is sampled at the falling
edge of VCLK. A high value sampled indicates that the next SCLK
rising edge should latch the high nibble of each byte of the pixel data
bus; a low value sampled indicates that the low nibble of each byte
of the pixel data bus should be latched (see Section 2.9). When the
general control register bit 3 = 0 and bit 2 = 0, the condition of
SFLAG/NFLAG is ignored. The condition of bit 3 = 1, bit 2 = 1 is not
allowed, and device operation is unpredictable when they are so set.
VCLK
78
L1
O Video clock output. VCLK is user-programmable output for
synchronization of the TLC34076 to a graphics processor.
VDD
45, 55, J1, L11, G12
57, 81
Power. All VDD terminals must be connected. The analog and digital
VDD terminals are connected internally.
{ Terminal numbers shown are for the FN package.
} Terminal numbers shown are for the GA package.
NOTES: 1. Although leaving unused terminals floating does not adversely affect device operation, tying unused
terminals to ground lowers power consumption, thus is recommended.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted.
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