TLC34076_16 Datasheet, PDF (19/69 Pages) Texas Instruments – Video Interface Palette

as a TTL-compatible input when the input clock selection register is so programmed. The clock source used
at power-up is CLK0; an alternative source can be selected by software during normal operation. This
chosen clock input is used unmodified as the dot clock (representing the pixel rate to the monitor). The
device does, however, allow for user programming of the SCLK and VCLK outputs (shift and video clocks)
using the output clock selection register. The input/output clock selection registers are shown in Tables 2– 3,
2– 4, and 2– 5.
Table 2–3. Input Clock Selection Register Format
BITS^†
3
2
1
0
FUNCTION^‡
0
0
0
0 Select CLK0 as clock source^§
0
0
0
1 Select CLK1 as clock source
0
0
1
0 Select CLK2 as clock source
0
0
1
1 Select CLK3 as TTL clock source
0
1
0
0 Select CLK3 as TTL clock source
1
0
0
0 Select CLK3 and CLK3 as ECL clock sources
† _{Register bits 4, 5, 6, and 7 are don’t care bits.}
‡ _{When the clock selection is altered, a minimum 30-ns delay is incurred before the}
new clocks are stabilized and running.
§ _{CLK0 is chosen at power-up to support the VGA pass-through mode.}
Table 2–4. Output Clock Selection Register Format
BITS ^†
5
4
3
2
1
0
FUNCTION^‡
0
0
0
X
X
X VCLK frequency = DOTCLK frequency
0
0
1
X
X
X VCLK frequency = DOTCLK frequency/2
0
1
0
X
X
X VCLK frequency = DOTCLK frequency/4
0
1
1
X
X
X VCLK frequency = DOTCLK frequency/8
1
0
0
X
X
X VCLK frequency = DOTCLK frequency/16
1
0
1
X
X
X VCLK frequency = DOTCLK frequency/32
1
1
X
X
X
X VCLK output held at logic high level (default condition)^§
X
X
X
0
0
0 SCLK frequency = DOTCLK frequency
X
X
X
0
0
1 SCLK frequency = DOTCLK frequency/2
X
X
X
0
1
0 SCLK frequency = DOTCLK frequency/4
X
X
X
0
1
1 SCLK frequency = DOTCLK frequency/8
X
X
X
1
0
0 SCLK frequency = DOTCLK frequency/16
X
X
X
1
0
1 SCLK frequency = DOTCLK frequency/32
X
X
X
1
1
X SCLK output held at logic level low (default condition)^§
† _{Register bits 6 and 7 are don’t care bits.}
‡ _{When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are stabilized}
and running.
§ _{These lines indicate the power-up conditions required to support the VGA pass-through mode.}
2–3