TLC34076_16 Datasheet, PDF (56/69 Pages) Texas Instruments – Video Interface Palette

3.7 Timing Diagrams
tsu1
th1
RS0 – RS3
Valid
tw1
tw2
RD,WR
ten
tdis
D0 – D7
(Output)
Data Out, RD Low
D(0In–_p^ÎÎDut7) ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎtdÎÎ1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
Data In,
WR Low
ÎÎ^tÎÎ^v ÎÎÎÎÎÎ
tsu2
th2
Figure 3–1. MPU Interface Timing
3–12