TLC34076_16 Datasheet, PDF (59/69 Pages) Texas Instruments – Video Interface Palette

Appendix A
SCLK/VCLK and the TMS340x0
While the TLC34076 SCLK and VCLK outputs are designed for compatibility with all graphics systems, they
are also tightly coupled with the TMS340x0 graphics system processors. All the timing requirements of the
TMS340x0 have been considered. However, there are a few points that need to be explained with regard
to applications.
VCLK
All the video control signals in the TMS340x0 (i.e., BLANK, HSYNC, and VSYNC) are triggered and
generated from the falling edge of VCLK. The fact that the TLC34076 uses the falling edge to sample and
latch the BLANK input gives users maximum freedom to choose the frequency of VCLK and interconnect
the TLC34076 with the TMS340x0 GSP without glue logic. Needless to say, the VCLK frequency needs to
be selected to be compatible with the minimum VCLK period required by the TMS340x0.
In the TMS340x0, the same VCLK falling edge that generates BLANK requests a screen refresh. When the
VCLK period is longer than 16 TQs (TQ is the period of the TMS340x0 CLKIN), it is possible that the last
SCLK pulse could be used falsely to transfer the VRAM data from memory to the shift register along with
the last pixel transfer. The first SCLK pulse for the next scan line would then shift the first pixel data out of
the pipe and the screen would then falsely start from the second pixel.
SCLK and SFLAG
The TLC34076 SCLK signal is compatible with current 10 ns and slower VRAMs. When split-shift register
transfers are used, one SCLK pulse has to be generated between the regular shift register transfer and the
split-shift register transfer to ensure correct operation. The SFLAG input is designed for this purpose.
SFLAG can be generated from a programmable logic array and triggered by the rising edge of the TR/QE
signal or the rising edge of the RAS signal of the regular shift register transfer cycle. TR/QE can be used
if the minimum delay from when the VRAM TRG signal goes high to SCLK going high can be met by the
programmable logic array delay; otherwise, RAS can be used.
A–1