TLC34076_16 Datasheet, PDF (29/69 Pages) Texas Instruments – Video Interface Palette

Table 2–7. True-Color Modes
MODE
MUX CONTROL REGISTER BITS^†
543210
DATA
BITS PER
PIXEL^‡
PIXEL
BUS
WIDTH
SCLK
DIVIDE
RATIO^§
OVERLAY
BITS PER
PIXEL (4)
PIXEL
LATCHING
SEQUENCE^¶
6#
6a
001000
15
16
1
1
1) P15 – P0
6b
001001
16
16
1
N/A
1) P15 – P0
6c
001010
15
32
2
1) P15 – P0
1
2) P31 – P16
6d
001011
16
32
2
N/A
1) P15 – P0
2) P31 – P16
6e
001110
24
32
1
8
1) P31 – P0
6f
001101
24
32
1
8
1) P31 – P0
† _{Bits 6 and 7 are don’t care bits.}
‡ _{This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,}
often referred to as the number of bit-planes. This may be color palette address data (modes 0 – 5) or DAC data
(mode 6).
§ _{The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per}
bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and eight
bit-planes, four pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but
must be written to the output clock selection register.
¶ _{For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are}
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 6d with a 32-bit pixel bus width, the rising edge of SCLK latches all the data
groups, and the pixel clock shifts them out in the order P15 – P0 and P31 – P16.
# _{Mode 6 is true-color mode in which 24 bits of color information are transferred directly from the pixel port to the DACs;}
overlay is implemented with the remaining 8 bits of the pixel bus. The distribution of pixel port data to the DACs is as
follows: P31 – P24 are passed to the blue DAC, P23 – P16 are passed to the green DAC, and P15 – P8 are passed
to the red DAC. P7 – P0 generate overlay data; this operation can be disabled by either grounding P7 – P0 or by clearing
the read mask (see subsection 2.4.6).
NOTE 1: Although leaving unused terminals floating does not adversely affect device operation, tying unused terminals
to ground lowers power consumption and is recommended.
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