TLC34076_16 Datasheet, PDF (39/69 Pages) Texas Instruments – Video Interface Palette

2.10 MUXOUT Output
MUXOUT is a TTL-compatible output. It is software programmable and controls external devices. Its typical
application is to select the HSYNC and VSYNC inputs between the VGA pass-through mode and the normal
modes. This output is driven low at power up or when the VGA pass-through mode is selected; at any other
time it can be programmed to the desired polarity through the general control register bit 7.
2.11 General Control Register
The general control register controls HSYNC and VSYNC polarity, split shift register transfer enabling,
special nibble mode, little-endian and big-endian modes, sync control, the ones-accumulation clock source,
and the VGA pass-through indicator. The bit field definitions are given in Table 2–11:
Table 2–11. General Control Register Bit Functions
GENERAL CONTROL REGISTER BIT
76543210
FUNCTION
X X X X X X X 0 HSYNCOUT is active-low
X X X X X X X 1 HSYNCOUT is active-high (default)
X X X X X X 0 X VSYNCOUT is active-low
X X X X X X 1 X VSYNCOUT is active-high (default)
X X X X X 0 X X Disable split shift register transfer (default)
X X X X 0 1 X X Enable split shift register transfer
X X X X 0 X X X Disable special nibble mode (default)
X X X X 1 0 X X Enable special nibble mode
X X X 0 X X X X 0-IRE pedestal (default)
X X X 1 X X X X 7.5-IRE pedestal
X X 0 X X X X X Disable sync (default)
X X 1 X X X X X Enable sync
X 0 X X X X X X Little-endian mode (default)
X 1 X X X X X X Big-endian mode
0 X X X X X X X MUXOUT is low (default)
1 X X X X X X X MUXOUT is high
2.11.1 HSYNCOUT and VSYNCOUT (Bits 0 and 1)
HSYNCOUT and VSYNCOUT polarity inversion is provided to allow indication to monitors of the current
screen resolution. Since the polarities for the VGA pass-through mode are provided at the feature connector,
the inputs to the TLC34076 already have right polarities for monitors, so the TLC34076 passes them through
with pipeline delay (see Section 2.8). These 2 bits work only in the normal modes, and the input horizontal
and vertical syncs are active-low incoming pulses. These 2 bits default to 1 but can be changed by software.
2.11.2 Split Shift Register Transfer Enable (SSRT) and Special Nibble Mode Enable
(SNM) (Bits 2 and 3)
Section 2.9 provides a detailed description for SSRT and SNM.
2.11.3 Pedestal Enable Control (Bit 4)
Bit 4 specifies whether a 0- or 7.5-IRE blanking pedestal is to be generated on the video outputs. Having
a 0-IRE blanking pedestal means that the Black and Blank levels are the same.
• 0 = 0-IRE pedestal (default)
• 1 = 7.5-IRE pedestal
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