TLC34076_16 Datasheet, PDF (14/69 Pages) Texas Instruments – Video Interface Palette

1.5 Terminal Functions (TLC34076C and TLC34076M)
TERMINAL
I/O
DESCRIPTION
NAME
NO.{
NO.}
I/O
DESCRIPTION
BLANK,
VGABLANK
60, 61 M9, L8
I Blanking inputs. Two blanking inputs are provided in order to remove
any external multiplexing of the signals that may cause data and
Blank to skew. When the VGA pass-through mode is set in the
multiplex control register, the VGABLANK input is used for blanking;
otherwise, BLANK is used.
CLK0 – CLK2 77, 76, K2, L2, K3
75
I Dot clock inputs. Any of the three clocks can drive the dot clock at
frequencies up to 135 MHz. When VGA pass-through mode is
active, CLK0 is used by default.
CLK3, CLK3 74, 73 M1, L3
I Dual-mode dot clock input. The clock input is an ECL-compatible
input, but a TTL clock may be used on either CLK3 or CLK3 when
so selected in the input clock selection register. This input may be
selected as the dot clock for any frequency of operation up to the
device limit. It can also be used with a single-ended ECL clock
source when the unused input is externally terminated to provide the
proper common mode level.
COMP
D0 – D7
52
K11
36 – 43
B12, C12,
D11, D12,
E11, E12,
F11, F12
I Compensation input. COMP provides compensation for the internal
reference amplifier. A resistor (optional) and ceramic capacitor are
required between COMP and VDD. The resistor and capacitor must
be as close to the device as possible to avoid noise pickup (see
Appendix B for more details).
I/O MPU interface data bus. D0 – D7 transfers data in and out of the
register map and palette/overlay RAM.
FS ADJUST 51
L12
I Full-scale adjustment. A resistor connected between FS ADJUST
and ground controls the full-scale range of the DACs.
GND
44, 54, J2, L10,
56, 80 K10, G11
Ground. All GND terminals must be connected together. The analog
and digital GND terminals are connected internally.
HSYNCOUT, 46, 47 H12, H11
VSYNCOUT
O Horizontal and vertical sync outputs. The HSYNCOUT and
VSYNCOUT are the true/complement gate mentioned in the
HSYNC and VSYNC description below (see Section 2.8).
HSYNC,
VSYNC
58, 59 M10, L9
I Horizontal and vertical sync inputs. HSYNC and VSYNC generate
the sync level on the green current output. They are active-low inputs
for the normal modes and are passed through a true/complement
gate. For the VGA pass-through mode, they are passed through to
HSYNCOUT and VSYNCOUT without polarity change as specified
by the control register (see Section 2.8).
IOR, IOG, IOB 48, 49, J12, J11,
50
K12
O Analog current outputs. The IOR, IOG, and IOB outputs can drive a
37.5-Ω load directly (doubly terminated 75-Ω line), thus eliminating
the need for any external buffering.
{ Terminal numbers shown are for the FN package.
} Terminal numbers shown are for the GA package.
NOTES: 1. Although leaving unused terminals floating does not adversely affect device operation, tying unused
terminals to ground lowers power consumption, thus is recommended.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted.
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