TI380C25 Datasheet, PDF (63/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

SBCLK
SAS ^†
SUDS,
SLDS
SRNW
SXAL
SALE
SADL0 – SADH7,
SADH0 – SADL7,
SPH, SPL
SDTACK ^§¶
SDDIR
SDBEN ^†
T4
TX
218
High
216
T1
S1
S2
TWAIT
V
T2
T3
S3
S4
S5
S6
T4
S7
222
210
223R
217
217
T1
209
209
216
218
212
233
233
Extended Address
212
233a
Address
214
247^‡
208a
208b
237R
205
Data In
216a
229
206
207a
Hi-Z
207b
225R
† _{On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data may be removed when either the read strobe or SDBEN becomes}
no longer active.
‡ _{If parameter 208a is not met, valid data must be present before SDTACK goes low.}
§ _{Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.}
¶ _{All VSS pins should be routed to minimize inductance to system ground.}
Figure 27. 68xxx-Mode DMA Read-Cycle Timing