TI380C25 Datasheet, PDF (27/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TI380C25
TOKEN-RING COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
SPWS012 – JANUARY 1995
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level
at which the signal is said to be high is 2 V, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
2 V (high)
0.8 V (low)
test measurement
The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of TI380C25 output signals.
Tester Pin
Electronics
IOL
VLOAD
Output
Under
Test
CT
IOH
Where: IOL
IOH
VLOAD
CT
= 2 mA, dc-level verification (all outputs)
= 400 µA (all outputs)
= 1.5 V, typical dc-level verification or
0.7 V, typical timing verification
= 65 pF, typical load-circuit capacitance
Figure 3. Test-Load Circuit
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