TI380C25 Datasheet, PDF (50/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode DMA write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
MIN
MAX
MIN
MAX
Setup time, asynchronous signal SRDY before
208a SBCLK no longer high to assure recognition on that
10
10
cycle
208b
Hold time, asynchronous signal SRDY after SBCLK
low to assure recognition on that cycle
10
10
212
Delay time, SBCLK low to SADH0 – SADH7,
SADL0 – SADL7, SPH, and SPL valid
20
20
216
Delay time, SBCLK high to SALE or SXAL high
20
20
216a Hold time, SALE or SXAL low after SWR high
0
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
25
0
25
218
Hold time, address valid after SALE, SXAL low
tw(SCKH) – 15 tc(SCK) / 2 – 4 tw(SCKH) – 15 tc(SCK) / 2 – 4
219
Delay time, SBCLK low in T2 cycle to output data and
parity valid
29
29
221
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL valid after SWR high
tc(SCK) – 12
tc(SCK) – 12
223W Delay time, SBCLK low to SWR high
0
16
0
11
225W Delay time, SBCLK high in T4 cycle to SDBEN high
16
11
Hold time, SDBEN low after SWR, SUDS, and SLDS
225WH _high
tc(SCK) / 2 – 7
tc(SCK) / 2 – 7
227W Delay time, SBCLK low in T2 cycle to SWR low
0
20
0
15
Setup time, SADH0 – SADH7, SADL0 – SADL7,
233
SPH, and SPL valid before SALE, SXAL no longer
10
10
high
237W Delay time, SBCLK high in T1 cycle to SDBEN low
16
11
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
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