TI380C25 Datasheet, PDF (48/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode DMA read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
MIN
MAX
MIN
MAX
Setup time, SADL0 – SADL7, SADH0 – SADH7,
205 SPH, and SPL valid before SBCLK in T3 cycle no
10
10
longer high
Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH,
206 and SPL valid after SBCLK low in T4 cycle if
10
10
parameters 207a and 207b not met
Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH,
207a _{and SPL valid after SRD high}
0
0
207b
Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH,
and SPL valid after SDBEN no longer low
0
0
Setup time, asynchronous signal SRDY before
208a SBCLK no longer high to assure recognition on this
10
10
cycle
208b
Hold time, asynchronous signal SRDY after SBCLK
low to assure recognition on this cycle
10
10
212 Delay time, SBCLK low to address valid
20
20
Delay time, SBCLK low in T1 cycle to
214† SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL in
20
15
the high-impedance state
216 Delay time, SBCLK high to SALE or SXAL high
20
20
216a Hold time, SALE or SXAL low after SRD high
0
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
25
0
25
218
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL valid after SALE or SXAL low
tw(SCKH) – 15
tc(SCK) / 2 – 4 tw(SCKH) – 15
tc(SCK) / 2 – 4
Delay time, SBCLK low in T4 cycle to SRD high
223R _{(see Note 21)}
0
16
0
11
225R Delay time, SBCLK low in T4 cycle to SDBEN high
16
11
Delay time, SADH0 – SADH7, SADL0 – SADL7,
226† SPH, and SPL in the high-impedance state to SRD
0
0
low
227R Delay time, SBCLK low in T2 cycle to SRD low
0
15
0
15
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH,
229† and SPL in the high-impedance state after SBCLK
0
0
low in T1 cycle
231 Pulse duration, SRD low
2tc(SCK) – 25
Setup time, SADH0 – SADH7, SADL0 – SADL7,
233 SPH, and SPL valid before SALE, SXAL no longer
10
high
2tc(SCK) – 25
10
237R Delay time, SBCLK high in the T2 cyle to SDBEN low
16
11
247
Setup time, data valid before SRDY low if parameter
208a not met
0
0
† _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
NOTE 21: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
48
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