TI380C25 Datasheet, PDF (36/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
memory-bus timing: write cycle
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
58 Setup time, MW low before MRAS no longer low
60 Setup time, MW low before MCAS no longer low
63 Setup time, valid data / parity before MW no longer high
64 Pulse duration, MW low
65 Hold time, data / parity out valid after MW high
66 Setup time, address valid on MAX0, MAX2, and MROMEN before MW no longer low
67 Hold time, MRAS low to MW no longer low
69 Hold time, MCAS low to MW no longer low
70 Setup time, MBEN low before MW no longer high
71 Hold time, MBEN low after MW high
72 Setup time, MDDIR high before MBEN no longer high
73 Hold time, MDDIR high after MBEN high
MIN
tM
1.5tM – 6.5
5.1
2.5tM – 9
0.5tM – 10.5
7tM –11.5
5.5tM – 9
4tM –11.5
1.5tM – 13.5
0.5tM – 6.5
2tM – 9
1.5tM – 12
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX0,
MAX2,
MROMEN
Address /
Enable
Address
MAXPH, MAXPL,
MADH0 – MADH7,
MADL0 – MADL7
Address
ADD / STS
Data / Parity Out
MRAS
MCAS
MW
MBEN
MDDIR
58
60
65
63
64
69
67
66
70
72
71
73
Figure 9. Memory-Bus Timing: Write Cycle
36
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