TI380C25 Datasheet, PDF (46/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode bus-arbitration timing, SIF takes control
25-MHz
33-MHz
NO.
OPERATION
OPERATION
MIN
MAX
MIN
MAX
208a
Setup time, asynchronous signal SBBSY and SHLDA before SBCLK no
longer high to assure recognition on that cycle
10
10
Hold time, asynchronous signal SBBSY and SHLDA after SBCLK low to
208b _{assure recognition on that cycle}
10
10
212
Delay time, SBCLK low to SADH0 – SADH7, SADL0 – SADL7, SPH, and
SPL valid
20
20
224a Delay time, SBCLK low in cycle I2 to SOWN low
0
20
0
15
224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
28
23
230 Delay time, SBCLK high to SHRQ high
20
15
241 Delay time, SBCLK high in TX cycle to SRD and SWR high, bus acquisition
25
25
241a†
Hold time, SRD and SWR in the high-impedance state after SOWN low,
bus acquisition
tc(SCK) _{– 15}
tc(SCK) _{– 15}
† _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
46
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