TI380C25 Datasheet, PDF (61/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

User Master
SIF Inputs:
( T4)
SBCLK
SBGR
Bus Exchange
I1
I2
TX
208a
208b
SIF Master
T1
T2
SBERR,
SDTACK,
SBBSY
SIF Outputs:
SBRQ ^†
SAS, SLDS,
SUDS
SRNW
SADH0 –
SADH7,
SADL0 –
SADL7,
SPH, SPL
SDDIR
SOWN ^‡
230
208a
Input
208b
212
Hi-Z
224c
224a
241a
230
241
Output
241
Read
Write
SIF
Write
Read
† _{In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface}
deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
‡ _{While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.}
Figure 26. 68xxx-Mode Bus-Arbitration Timing, SIF Takes Control