TI380C25 Datasheet, PDF (49/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TWAIT
T4
TX
T1
T2
V
T3
T4
T1
SBCLK
SRAS
SBHE ^†
Hi-Z
212
Valid
SWR
SRD ^‡
SXAL
SALE
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL ^§
216
217
216
233
212
218
Extended
Address
227R
218
217
High
226
212
214
233
Address
218
205
247
208a ^¶
Data
223R
216a
207a
206
207b
229
Address
SRDY
SDBEN ^‡
237R
208b
225R
SDDIR
Low
† _{In 8-bit 80x8x mode, SBHE / SRNW is a don’t care input during DIO and an inactive (high) output during DMA.}
‡ _{Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.}
§ _{In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held after T4 high.}
¶ _{If parameter 208A is not met, valid data must be present before SRDY goes low.}
Figure 19. 80x8x-Mode DMA Read-Cycle Timing