TI380C25 Datasheet, PDF (12/71 Pages) Texas Instruments – TOKEN-RING COMMPROCESSOR

TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
NAME
NO.
SRESET
44
I / O^†
I
DESCRIPTION
System reset. SRESET is activated to place the TI380C25 into a known initial state. Hardware reset
puts most of the TI380C25 outputs into the high-impedance state and places all blocks into the reset
state. The Intel mode DMA bus-width selection (S8) is latched on the rising edge of SRESET.
H
= No system reset
L
= System reset
Rising edge = Latch bus width for DMA operations (for Intel-mode applications)
Intel Mode
SRSX and SRS0 – SRS2 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS2 (see Note 1).
MSb
Register selected = SRSX
SRS0
SRS1
LSb
SRS2 / SBERR
SRSX
47
SRS0
46
SRS1
45
SRS2 / SBERR
54
SRSX, SRS0 and SRS1 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
I
SRSX and the least significant bit is SRS1 (see Note 1).
Motorola
Mode
MSb
Register selected = SRSX
SRS0
LSb
SRS1
SBERR is used for bus error. This signal corresponds to the bus-error signal of the 68xxx
microprocessor. SBERR is internally synchronized to SBCLK. This input is driven low
during a DMA cycle to indicate to the TI380C25 that the cycle must be terminated ( see
Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s Guide
(SPWU005) for more information).
SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe
that is an input during DIO and an output during DMA.
SWR / SLDS
Intel Mode _{H = Write cycle is not occurring.}
L = If DMA, data to be driven from SIF to host bus.
61
I/O
If DIO, on the rising edge, the data is latched and written to the selected register.
Motorola
Mode
SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an
output during DMA.
H = Not valid data on SADL0 – SADL7 lines
L = Valid data on SADL0 – SADL7 lines
SXAL
System-extended-address latch. SXAL provides the enable pulse used to externally latch the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle
63
O
of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address
counter causes a carry out of the lower 16 bits). Systems that implement parity on addresses can use
SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.
SYNCIN
136
I
Reserved. SYNCIN must be left unconnected (see Note 1).
† _{I = input, O = output}
NOTES: 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.
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