TCA5013 Datasheet, PDF (58/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
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10 Power Supply Recommendations
The TCA5013 has two power supplies V_DD and V_DDI. When the device is powering up, the ramp rates of V_DD and
V_DDI can cause the supervisor fault to be asserted. The supervisor fault at power up can be avoided if V_DD is
ramped and stable before V_DDI is ramped.
10.1 Power-On-Reset
When the voltage on these pins ramps an internal power-on-reset circuit holds the device in reset condition
unless the voltage on both pins rises above the VPORR voltage defined Table 13. Values in Table 13 are
ensured by design, but are not tested in production.
PARAMETER
V_PORF
V_PORR
Table 13. Power On Reset Thresholds
DESCRIPTION
Voltage trip point of POR on falling V_DD
Voltage trip point of POR on falling V_DDI
Voltage trip point of POR on rising V_DD
Voltage trip point of POR on rising V_DDI
MIN
TYP
1.8
1.85
1.4
1.5
1.9
1.95
1.45
1.5
MAX
1.95
1.55
2
1.55
UNIT
V
V
V
V
11 Layout
11.1 Layout Guidelines
11.1.1 DC-DC Boost Layout Recommendation
Some key guidelines are listed here to be followed for the layout of the DC-DC boost in the TCA5013:
• The inductor must be placed close to the LX pin such that the trace resistance between the LX pin and the
inductor terminal is as small as possible.
• The 10 µF input capacitor on VDD shall be placed close to the inductor terminal and the two shall be
connected by a copper pour to minimize resistance as much as possible.
• The other terminal of the 10 µF capacitor should be connected to GNDP plane by multiple vias to provide a
low resistance path to ground.
• The 100 nF capacitor should be placed as close to VDD pin as possible.
• The anode of the schottky diode shall be placed as close as possible to the inductor and shall be connected
to it by a copper pour to minimize resistance as much as possible.
• The 10 µF output capacitor on VUP should have a very low resistive connection to VUP and GNDP.
11.1.2 Card Interface Layout Recommendations
The card interface layout is important for proper operation of the device and for meeting EMV4.3 electrical
requirements:
• If possible two 100 nF capacitors should be connected to VCC. One near the TCA5013 and one close to the
card slot.
• If only one 200 nF capacitor is used it should be placed close to the TCA5013.
• If possible the CLK trace should be routed on a separate signal layer different from the layer on which the
other card interface traces (IO and RST) are routed. It is also recommended that the two signal layers be
separated by a ground plane if possible.
• The GNDS, GNDUC and GND pins should be connected to the ground plane with the shortest trace possible
to reduce inductance from the device ground to the ground plane. This is critical in order for the device to
meet the 8 kV IEC protection level on the card interface pins.
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