TCA5013 Datasheet, PDF (30/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
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Power on reset
VDD /
VDDI
PRES
Debounce period
100 us
Card extracted
Card slot
deactivated
POR interrupt
INT
PRES bit = 1
Debounce period
20 ms
PRESL
Interrupt
PRES bit = 0
Interrupt
I ²C
status
register
read
Figure 14. Device Power up with Card Inserted In System - High to Low PRES Topology
8.4.6 IO Operation
All card interfaces in the TCA5013 have an IO pin that connects data, to and from the microcontroller, with the
smartcard. The TCA5013 provides automatic level translation from IOMC pin operating voltage (V_DDI) to the
voltage at which the card is activated (V_CC).
8.4.6.1 IO Switching Control
The card interface IOs (IOUC, IOS1, IOS2 and IOS3) connect to the IOMC1 and IOMC2 through switches inside
the TCA5013.
The IOUC pin is connected to IOMC1 through an SPST (single-pole single-throw) switch. The switch is controlled
by the IO_EN_UC bit (Reg 0x01, Bit 5).The IO_EN_UC bit shall be set to 1 before card activation is started to
ensure that the host processor is able to receive the ATR response from the smartcard. When an I2C command
is received to open or close the switch, it is immediately implemented regardless of the status of IOUC or IOMC1
pins. It is therefore possible that the switch opens or closes during a rising or falling edge, which could result in a
glitch on the IOUC or IOMC1 pins.
The IOS1, IOS2 and IOS3 all are connected to IOMC2 through a SP3T (single-pole triple-throw) switch, such that
only one of the SAM interfaces can be connected to IOMC2 at any one time. The connection between the
IOMC2 and the SAM card IO pins is controlled by IO_EN_S1 (Reg 0x11, Bit 5), IO_EN_S2 (Reg 0x21, Bit 5),
IO_EN_S3 (Reg 0x31, Bit 5). If any one of the IO_EN bits is set for example, if SAM1 is initially connected by
setting IO_EN of the SAM1 interface settings register to 1. When the IO_EN bit of the SAM2 or SAM3 is set to 1,
the SAM1 gets disconnected and its IO_EN bit will be set to 0. Only one SAM can be connected to the IOUC2 at
one time and whenever the IO_EN bit of any SAM interface settings register is set to 1, all other IO_EN bits get
cleared (set to 0). Similar to the user card, the SAM IO mux can also result in a short duration pulse, if IOUC2 is
not in the same state as the SAMs being switched to/from. Also when making the switch, the TCA5013 uses a
break –before-make switch topology in order to avoid any glitches on the lines due to the switching itself.
8.4.6.2 IO Rise Time and Fall Time control
The rise time and fall time of the card interface IO pins can be controlled using the IO slew rate settings register
(Reg 0x07 for user card and Reg 0x17 for SAMs). The EMV4.3 specification, has strict restrictions on signal
perturbations (overshoot and undershoot during transition). Controlling the rise time and fall time of the signals
can help to meet these requirements.
Table 6 shows the typical IO rise time for different register settings (based on a typical 30 pF load).
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