TCA5013 Datasheet, PDF (21/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

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TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
Device Functional Modes (continued)
Once synchronous type 1 activation has been initiated, the following sequence of events occurs on the user card
interface:
• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
• V_CC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
• After V_CC is stable RSTUC and CLKUC pulses are applied per t_S1-RST-HI and t_S1-CLK-HI defined in Table 2.
• After V_CC is stable, the IOUC line is pulled up to V_CC .
• After V_CC is stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg
0x09).
• RSTUC is held low while the CLKUC line starts oscillating with a frequency of ~40Khz (generated from
internal oscillator).
• The IO line is sampled on the 32 rising or falling (based on bit[1]; Reg 0x09) edges of CLK and stored in the
FIFO registers 0AH to 0DH.
• At the end of the 32nd CLK pulse, the CLKUC is held low and the CLKUC pin is controlled by the clock
settings register (Reg 0x02).
• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
• IOMC1 shall stay pulled up to V_DDI i.e. IOMC1 shall not be pulled low until INT is asserted.
• CLKIN1 shall toggle only after INT is asserted.
• RSTUC is controllable by I²C after INT is asserted.
Table 2. Synchronous Type 1 Card Activation Timing Characteristics
t_S1-RST-HI
t_S1-CLK-HI
t_S1-RST-CLK
t_S1-CLK-RST
t_S1-CLK-LO
t_S1-CLK-PER
Duty cycle
MIN TYP MAX UNIT
60 70
80
µs
10 12.5 15
µs
25 28
32
µs
25 28
32
µs
70 80
90
µs
22.5 25 27.5 µs
45 50
55
%
8.4.4.3 Synchronous Type 2 Operating Mode
Synchronous type 2 operating mode is only supported on the user card interface. To enter synchronous
operating mode, the user card interface goes through the synchronous type 2 activation sequence. Figure 5
shows the synchronous type 2 activation sequence.
CLKIN1 shall be low before the synchronous type 2 activation sequence is initiated. The following bit settings are
required to initiate a synchronous type 1 activation sequence.
• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
• CARD_TYPE (bit [7]; Reg 0x09) = 1
• START_SYNC (bit [0]; Reg 0x09) = 1
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