TCA5013 Datasheet, PDF (34/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
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Unlike all the other bits that control the CLK, the CLK_ENABLE_SYNC can cause the CLK state to transition
instantly. This means that when switching from a static level to a toggling CLK (or vice-versa), there can be
partial pulses (glitches) on the CLK output when CLK_ENABLE_SYNC is switched. In sync mode, the CLK
output can be switched directly from one static level to another, by using the CLK settings register (when
CLK_SYNC_ENABLE = 0).
CLK_ENABLE_SYNC
0
0
1
Table 9. Card CLK Truth Table in Synchronous Mode
BIT 7
X
X
X
CARD CLOCK SETTINGS REGISTER
BIT 6
BIT 5
BIT 4
BIT 3
1
X
X
X
0
X
X
X
X
X
X
X
BIT 2
X
X
X
CARD CLK OUTPUT
1
0
CLKIN1
8.4.7.2 CLK Rise Time and Fall Time Control
The clock slew rate setting register (Reg 0x08 for user card and Reg 0x18 for SAM) is used to control the rise
and fall time of the CLK pin. Table 10 shows the rise and fall time corresponding to each register setting. The
EMV4.3 specification, has strict restrictions on signal perturbations (overshoot and undershoot during transition).
Controlling the rise time and fall time of the CLK signals can help to meet these requirements.
Table 10. CLK Rise and Fall Time Settings
CLOCK SLEW RATE SETTINGS
REGISTER
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TYPICAL RISE TIME and FALL
RATE
6
7
9
11
13
14
15
16
17
18
19
20
21
22
23
25
8.4.7.3 Current Limiting On CLK Pin
The card CLK pins have a current limiting feature that prevents excess current from being drawn on them. When
an external load tries to draw a current higher than the limit, the device responds by adjusting the V_OH or V_OL to
limit the current. The device does not deactivate the card interface when over current limit of the CLK pins are
reached.
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