TCA5013 Datasheet, PDF (31/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

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TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
Table 6. IO Rise Time Register Settings
IO SLEW RATE SETTINGS
REGISTER BIT [7:5]
000
001
010
011
100
101
110
111
TYPICAL RISE TIME (ns)
60
60
80
80
100
100
120
120
Table 7 shows the typical IO fall time for different register settings (based on a typical 30 pF load). It should also
be noted that the output low logic level (V_OL) is affected by the fall time settings. As the fall time becomes slower
(higher value of fall time) the V_OL will be higher. Therefore, it is recommended that the fastest fall time setting
(smallest fall time value) for IO be used whenever possible. Table 7 also shows which settings are usable for the
different V_CC voltages, without risk of violating the V_OL levels required by the EMV4.3 and ISO7816
specifications.
Table 7. IO Fall Time Register Settings
IO SLEW
RATE
SETTINGS
REGISTER
BIT [4:3]
00
01
10
11
TYPICAL FALL
TIME (ns)
68
51
34
17
V_CC = 5 V
Usable
Usable
Usable
Usable
V_CC = 3 V V_CC = 1.8 V
Not usable
Not usable
Usable
Usable
Not usable
Not usable
Not usable
Usable
8.4.6.3 Current Limiting on IO Pin
The card IO pins have a current limiting feature that prevents excess current from being drawn on them. The
actual current limit can vary based on the fall time setting used for the IO pin, but it is always within the limits
defined in Electrical Characteristics—Fault Condition Detection. When an external load tries to draw a current
higher than the limit, the device responds by adjusting the V_OH or V_OL to limit the current. The device does not
deactivate the card interface when over current limit of the IO pins are reached.
8.4.7 CLK Operation
All card interfaces in the TCA5013 have a CLK pin that provides a clock signal to the smartcard. The TCA5013
provides automatic level translation of the CLK signal from the CLKIN1/CLKIN2 operating voltage (V_DDI) to the
voltage at which the card is activated (V_CC).
8.4.7.1 CLK Switching
The CLK output on each of the smartcard interfaces can be controlled by the corresponding clock settings
register (Reg 0x02 for user card, Reg 0x12 for SAM1, Reg 0x22 for SAM2, Reg 0x32 for SAM3). The CLKIN1
pin is dedicated for the user card interface while The CLKIN2 is shared between the SAM interfaces. The clock
settings register allows the CLK output to be configured in one of 4 different modes.
1. CLK 0 mode - The CLK output of the card interface is static low.
2. CLK 1 mode - The CLK output of the card interface is static high.
3. CLK div mode - The CLK output is a divided down frequency of the CLKIN1 or CLKIN2 frequency. Bit [4:2] of
clock settings register defines the division ratio.
4. Internal CLK mode - The CLK output is at a fixed frequency (~1.2 MHz) based off the internal oscillator.
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