TCA5013 Datasheet, PDF (33/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

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TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
Internal
Clock
External
Clock
Clock
Output
Figure 16. Output CLK Frequency Transition When Switching From External Clock to Internal Clock
In CLK divide mode, when CLKIN/2, CLKIN/4 or CLKIN/8 division ratios are used, the output duty cycle is not
affected by the duty cycle of the input clock on CLKIN. When the CLKIN/1 and CLKIN/5 division ratios are used,
the output clock duty cycle is a function of the CLKIN1/CLKIN2 duty cycle. For CLKIN/1 the output duty cycle will
be equal to the input duty cycle. For CLKIN/5 the output CLK duty cycle is given by (n+2) / 5, where n is the duty
cycle of the input clk; for example, if the input clk has a 40% duty cycle (n = 0.4) the CLKIN/5 output will have a
(0.4+2) / 5 = 0.48 or 48% duty cycle. In addition to asynchronous mode, the user card interface can also operate
in synchronous mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating
Mode).When in synchronous mode the user card CLK pin output is controlled by CLK_ENABLE_SYNC (bit [2],
Reg 0x09) in addition to the clock settings register. Figure 17 shows a simplified logical representation of the
user card clock muxing circuit.
User card Clock
settings register
CLKIN1
0
1
CLKIN1/8
CLK ^CLKIN1/5
divider CLKIN1/4
circuit _CLKIN1/2
CLKIN1/1
Internal
Oscillator
User card Clock
settings register
Bit [6:5]
0 [1:x]
1 [0:x]
0
1
Async
CLK_UC
Sync
Sync mode/
Async Mode
CLK_SYNC_ENABLE
Figure 17. Clock Muxing Logic in Synchronous Mode
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