TCA5013 Datasheet, PDF (32/68 Pages) Texas Instruments – Feature Rich Smartcard Interface IC

TCA5013
SCPS253B – JANUARY 2014 – REVISED JANUARY 2016
www.ti.com
The allowable changes in CLK output can vary depending on the mode in which the interface has been
activated. In asynchronous mode (see Asynchronous Operating Mode), The CLK output can be dynamically
switched from one state to another. Table 8 shows the permitted frequency transitions on CLK pin in
asynchronous mode. Any I²C command that attempts to switch the CLK frequency outside of these state
transitions can result in the change not happening on the output or other unpredictable behavior that could cause
device to lock up. If the device enters such a locked state, it can be reset by toggling SHDN pin.
Table 8. Permitted CLK Switching Operations in Asynchronous Mode
FROM
Internal CLK
Internal CLK
Internal CLK
CLK div
CLK div
CLK div
CLK 0
CLK 0
CLK 0
CLK 1
CLK 1
CLK 1
TO
CLK div
CLK 0
CLK 1
Internal CLK
CLK 0
CLK 1
CLK div
Internal CLK
CLK1
CLK div
Internal CLK
CLK 0
Permitted
Not Permitted
Not Permitted
Permitted
Permitted
Permitted
Permitted
Not Permitted
Not Permitted
Permitted
Not Permitted
Not Permitted
When command sets the device in Internal clock mode or CLK 0 mode or CLK 1 mode, the division ratio is
locked out, that is, when an I²C transaction that sets either one of the bits [7:5] of the card clock settings register
to 1, the remaining bits in the register (bit [4:2]) will not not be updated. It is to be noted that an asynchronous
activation cannot be performed with the internal clock. At the start of the asynchronous activation, if the internal
CLK mode is selected in the clock settings register, then the device shall begin activation based on divide ratio
defined by bit [4:2] of clock settings register. After the activation is completed, the CLK output will switch to
Internal CLK mode. When switching to/from a CLK div mode from/to CLK 0 mode or CLK 1 mode, the device
waits for the input clock (CLKIN1 or CLKIN2) phase to match the static level it will switch to/from and then makes
the transition to ensure that no partial pulses or glitches are seen on the output clock. Similarly, when switching
from one division ratio to another the change happens on the rising clock edges to ensure no glitch on the
output. Figure 15 shows how the change in divide ratio is seen on the CLK pin.
CLKINx/2
CLKINx/4
Output clock frequency transition when changing clock divide ratio
Figure 15. CLK Divide Ratio Change on Card CLK Output
When switching from CLK divide mode to the Internal CLK mode, the device waits for the edges of the internal
and external clock to line up (fall within ~10 ns of each other) and makes the switch on that edge. If the external
clock is close to an exact harmonic of 1.2 MHz, there could be a situation where the rising edges of the two
clocks take very long (milliseconds or seconds) to line up and this would mean the frequency switch at the output
would happen long after the I²C command to make the switch is issued. The CLKSW bit (bit [3]) in the card
interface status register (Reg 0x01 for user card, Reg 0x11 for SAM1, Reg 0x21 for SAM2, Reg 0x31for SAM3)
is set when the internal clock frequency is seen on the CLK pin.
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